Electronic circuits, such as integrated circuits (ICs), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating IC devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of the circuit, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design.
Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.” Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.
Once the components and their interconnections are established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to manufacture the circuit. Typically, a designer will select groups of geometric elements representing IC components (e.g., contacts, channels, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines are then routed between the geometric elements, which will form the wiring used to interconnect the electronic devices. Layout tools (often referred to as “place and route” tools), such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for both of these tasks.
Circuit layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional (2D) graphical circuit layout data. Among other features, it contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Mentor Graphics, Inc., and the more recent Open Artwork System Interchange Standard (OASIS) proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in layout designs that are employed to manufacture integrated circuits. Once the design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the circuit using a photolithographic process.
There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.
Each time that a layer of material is exposed to radiation, a mask must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in a layout design define the relative locations or areas of the circuit that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the layout design, after which the mask can be used in a photolithographic process.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate (and thus the shapes in the mask) become smaller and are placed closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the layout design onto the substrate. The diffractive effects of light often result in defects where the intended image is not accurately “printed” onto the substrate during the photolithographic process, creating flaws in the manufactured device. One or more resolution enhancement techniques (RETs) are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process. Examples of various resolution enhancement techniques are discussed in “Resolution Enhancement Technology: The Past, the Present, and Extensions for the Future,” Frank M. Schellenberg, Optical Microlithography XVII, edited by Bruce W. Smith, Proceedings of SPIE Vol. 5377, which article is incorporated entirely herein by reference.
One of these techniques, “optical proximity correction” or “optical process correction”(OPC), adjusts the amplitude of the light transmitted through a lithographic mask by modifying the layout design data employed to create the mask. For example, edges in the layout design may be adjusted to make certain portions of the geometric elements larger or smaller, in accordance with how much additional light exposure (or lack of exposure) is desired at certain points on the substrate. When these adjustments are appropriately calibrated, overall pattern fidelity is greatly improved.
Off-axis illumination (OAI) is another widely used RET, taking advantage of the relationship between image resolution and the propagation direction of the light transmitted through a lithographic mask. OAI improves the image resolution by shifting diffraction orders such that higher order diffraction beams can be collected by the collection pupil of the objective lens. A particular oblique illumination direction improves resolution of only those features that are correctly oriented with respect to that illumination direction, however. Consequently, different layout features may require different OAI light sources. A category of OAI light sources is dipole light sources. Examples of two such dipole light sources are illustrated in FIG. 5. Dipole illumination increases image resolution of layout features that are oriented perpendicular to the axis of the dipole, but results in a significantly degraded image contrast for layout features that are parallel to the axis of the dipole.
A double exposure technique known as double dipole lithography (DDL) has been developed to utilize the benefits of dipole illumination and at the same time to reduce the degrading effects. In DDL, the layout design data are decomposed into two layout portions, corresponding to two dipole light sources with orthogonal dipole orientations. The two layout portions are then used to fabricate two masks. To simplify the description, an X dipole light source 501 and a Y dipole light source 503 are used here to denote the two light sources with orthogonal dipole orientations, as illustrated in FIG. 5. The two layout design portions are labeled as a vertical layout portion and a horizontal layout portion. The mask made with the vertical layout portion is exposed by the X dipole light source and the second mask made with the horizontal layout portion is exposed by the Y dipole light source. Accordingly, DDL uses two masks and two exposures followed by a single etch to print one layer of layout features onto a substrate. It should be appreciated that the two pairs of words, “X/Y” and “vertical/horizontal” are used to describe orientations relative to each other, not specific orientations.
The layout decomposition for DDL is not as straightforward as it appears to be. Many features may not be classified as either horizontal or vertical layout features. It is particularly true for low aspect ratio features such as small jog, line-ends, and landing pads. Effects of neighboring features may also need to be considered. Thus, the layout decomposition remains a challenge in DDL.